![positive edge triggered flip flop in verilog positive edge triggered flip flop in verilog](https://4.bp.blogspot.com/-7IA0Y3PyLmc/VDIq7yK3VrI/AAAAAAAAAZA/XIgsY8xhSYU/s640/Block%2BDiagram.png)
#POSITIVE EDGE TRIGGERED FLIP FLOP IN VERILOG CODE#
In order to simulate our design, we have to place the module of our verilog code inside a testbench. The expression simply takes sig and does a logical AND with the inversion of sig. Hence we have used the assign statement to assign an expression to pe. Output pe is an implicit variable of type wire and can be assigned only by a continous assignment. We create an internal signal called sig_dly of type reg that can store a single clock cycle delayed version of sig, and is achieved by the always block.
![positive edge triggered flip flop in verilog positive edge triggered flip flop in verilog](https://i.imgur.com/ZviMF2o.png)
So we expect to see a pulse on pe whenever sig changes from value 0 to 1. The design aims to detect the positive edge of input sig, and output pe. The module shown above is named pos_edge_det and has two inputs and one output. Assign statement assigns the evaluated expression in the RHS to the internal net pe Combinational logic where sig is AND with delayed, inverted version of sig This always block ensures that sig_dly is exactly 1 clock behind sig Reg sig_dly // Internal signal to store the delayed version of signal Output pe) // Output signal that gives a pulse when a positive edge occurs Module pos_edge_det ( input sig, // Input signal for which positive edge has to be detected The idea behind a positive edge detector is to delay the original signal by one clock cycle, take its inverse and perform a logical AND with the original signal. A positive edge detector will send out a pulse whenever the signal it is monitoring changes from 0 to 1 (positive edge).